1. Field of the Invention
The present invention relates to the field of packaging integrated circuits and more specifically for use in surface mounting technology.
2. Prior Art
Various semiconductor housing structures and techniques are known in the prior art. In the packaging of integrated circuits, a die which comprises the integrated circuits is mounted onto a base wherein contact points face upward so that these contacts are exposed. A lead frame is utilized to provide the electrical coupling to the integrated circuit. Typically, the lead frame assembly is planar in construction and surrounds the die element. In some instances the lead frame forms the base upon which the die is disposed. The die contacts are coupled to the lead frame by wires or conducting tapes. Then, the whole assembly is encapsulated using a known encapsulating technique. These encapsulating techniques include the use of plastics and ceramics. Where hermetic sealing is desired, specialized encapsulation techniques are utilized. The lead ends of the lead frame are then formed to extend beyond the encapsulation, such that these leads provide the electrical coupling of the die to the external environment.
Integrated circuit packages are provided in a number of industry standard configurations. These include dual-in-line (DIP), pin grid array (PGA) and flat-pack packages. Then, the package is typically mounted onto a printed circuit board by known techniques. These techniques include inserting the leads into holes provided on the printed circuit board or, alternatively, the leads can have a surface mounting configuration where the leads do not extend into the circuit board.
A problem with the prior art packaging technique is the time and difficulty involved in precisely bonding lead wires from the integrated circuit to the lead frame. Lead count to die size ratio for of the package is a limiting factor with prior art techniques. Further, because the prior art techniques utilize a lead frame which surrounds the integrated circuit and lead wires are coupled to the ends of the lead frame, it is difficult or impossible, in some instances, to place multiple integrated circuit dies using a single lead frame assembly.
It is appreciated then that what is required is an integrated circuit packaging technique that is capable of housing an integrated circuit more efficiently and reliably then the prior art technique. Further, it is appreciated that a packaging technique which permits multiple integrated circuits to be housed in a singular package or provides a small die with a high lead count is needed.